1. Field of the Invention
The present invention relates to a voltage regulator that is to output a constant voltage regardless of the variations in power voltage supplied or load current outputted, and more particularly to the reduction of current consumption in the power save mode thereof.
2. Description of the Related Art
FIG. 1 is a configuration diagram of an existing voltage regulator.
The voltage regulator is configured with a reference voltage circuit 1 that generates a reference voltage REF based on a band gap, etc., an operational amplifier (OP) 2 that compares the reference voltage REF with a monitor voltage VM and outputs a detection voltage VD according to the difference thereof, a P-channel MOS transistor (hereinafter, referred to as “PMOS”) 3 connected between a power voltage VDD externally supplied and an output node N outputting a constant internal power voltage REG, in a manner controlled in conduction by a detection voltage VD, and a voltage-dividing circuit of resistances 4, 5 connected between the output node N and the ground voltage GND and for outputting a monitor voltage VM in a magnitude the internal power voltage is voltage-divided.
In the voltage regulator, when the resistances 4, 5 have respective values R4, R5, the monitor voltage VM is given as REG×R5/(R4+R5). The monitor voltage VM is provided to an inverting input terminal “+” of the operational amplifier 2 while the reference voltage REF is provided to a non-inverting input terminal “−” of the operational amplifier 2.
In this case, when the internal power voltage REG changes due to the variation in the power voltage VDD or load current flowing through the output node N thereby the monitor voltage VM becomes higher than the reference voltage REF, which causes an increase in the detection voltage VD outputted from the operational amplifier 2. This increases the on-resistance of the PMOS 3 and decreases the internal power voltage REG on the node N. Conversely, when the monitor voltage VM becomes lower than the reference voltage REF, there is a decrease in the detection voltage VD outputted from the operational amplifier 2, to decrease the on-resistance of the PMOS 3. This increases the internal power voltage REG on the node N. By such a feedback operation, the monitor voltage VM is controlled equal to the reference voltage REF. Accordingly, the internal power voltage REG is maintained constant at voltage REF×(R4+R5)/R5 on the output node N regardless of the variations in the power voltage VDD or the load current flowing through the output node N.
Furthermore, the related art is disclosed in Japanese Patent Kokai No. 2001-211640, for example.